Memory devices are known in the art and used in, among other things, virtually all microprocessor and digital signal processor applications. One such type of memory is SRAM. SRAM devices are fast and easy to use compared to many other types of memory devices, in part because they do not have to be frequently refreshed to maintain their contents. In addition, SRAM devices that use metal-oxide-semiconductor (MOS) technology exhibit relatively low standby power and do not require a refresh cycle to maintain stored information. These attributes make SRAM devices particularly desirable for portable equipment, such as laptop computers and personal digital assistants.
SRAM devices typically comprise columns of memory cells that span opposing bit lines (termed “bit” and “bit_”). The bit lines couple the memory cells to a sense amplifier that senses values stored in the cells. To sense the value stored in a cell, both the bit line and the bit_line are pre-charged to a predetermined voltage (termed VDD, which is a power supply voltage of the SRAM device), and the cell being read reduces the voltage of either the bit line or the bit_line based on the value stored in the cell. The sense amplifier determines which of the bit line or the bit_line is biased higher and generates a corresponding signal. Typically, the voltage difference between the bit line and bit_line voltage signals ranges between 50 mV and 100 mV. That is, as the voltage difference decreases to less than about 50 mV, it becomes increasingly difficult to discriminate accurately between the bit line and bit_line signals.
A continuing concern with SRAM (and most other MOSFET) devices is current leakage when transistor gates in the devices are biased in the off state. For example, current leakage from multiple cells in a given column can undesirably aggregate on the bit line or bit_line, whichever the case may be. During a READ, the opposing bit lines are both precharged to a high voltage and then one or the other is pulled low by the READ current of the addressed memory cell, depending on the state of the address memory cell. Thus a differential voltage is established on the opposing bit lines and the sense of the differential reflects the state of the addressed memory cell. At the same time as the READ current from the addressed memory cell is lowering the voltage of one of the bit lines, the leakage current from the unaddressed cells is lowering the voltage of the bit lines, again depending on the state for the unaddressed memory cells. If the majority of the leakage current is to the bit line opposite to the bit line being pulled low by the addressed memory cell, the leakage current will delay the establishment of a differential voltage adequate for sensing. In fact, if the aggregate of the leakage current to the opposite bit line is equal to or greater than the READ current, a proper differential will never be established. Current leakage therefore has the effect of prolonging the time required to accrue a sufficient voltage differential between the bit line and bit_line values so the sense amplifier can act.
Those skilled in the art understand that transistors having relatively higher threshold voltages experience relatively less current leakage. However, such transistors also experience relatively slower switching speeds that may be below design objectives. It thus follows that transistors having threshold voltages that are lower than optimal values for low leakage are required to meet switching speed requirements. Unfortunately, transistors having lower threshold voltages require significantly greater power due to much higher current leakage. In an attempt to overcome this dichotomy between fast switching transistors and those that experience less current leakage and require less power, designers have developed asymmetric SRAM cells in which one or more columns have higher threshold transistors connected to one bit line and lower threshold transistors connected to an opposing bit line.
For example, transistors on a “slow” side of a given column may have a high threshold voltage and thus a lower READ current but also a lower leakage to the bit line, and transistors on a “fast” side of the column may have a low threshold voltage and thus a larger READ current but also a larger leakage current to the bit line. In an attempt to compensate for the disproportionate READ current (and thus a disproportionate time to establish a given voltage differential between the bit lines), existing sense amplifiers have been configured to anticipate which of the bit lines is coupled to the fast or slow side of the memory cell. Accordingly, despite the requirement for special sense amplifiers, such configurations may result in an improved device wherein the balance between the power savings of high threshold transistors and the speed of low threshold transistors can be optimized.
However, the effect of the leakage current compared to the READ current must be taken into account. For example, consider an SRAM column with symmetrical cells. If the sense amplifier is trying to read a “one” (high voltage level) out of one cell in a column of 512 cells, and the 511 remaining cells are “zeros” (low voltage levels), the leakage from the 511 cells not being accessed affects the read time on the accessed cell based on the ION:IOFF ratio of the pass gates. If the ION:IOFF ratio were about 100:1, the current leakage from 100 cells equals the current of the one cell actually being accessed. Accordingly, it would be difficult to have more than about 64 rows in the column (64 being the highest number that is a power of two that is less than 100); the resulting device would be impractically slow.
However, if the ION:IOFF ratio were about 1000:1 (which is a more realistic worst case), the current leakage from 500 non-accessed cells would be about 50% of the current read from a single cell, thereby doubling the amount of time that it takes to read the accessed cell. The limitation in the number of rows caused by leakage current can be worse for the asymmetrical cell case where there is a fast bit line and a slow bit line. The READ current on the slow side must be compared to the leakage current on the fast side. If the aggregate leakage on the fast side (which has high leakage) is greater than the READ current on the slow side (which has the low READ current), a READ error may occur. Obviously, this would eliminate the advantage of having an asymmetrical cell.
Thus, cumulative current leakage in long columns of memory cells can negate the speed advantage of having relatively low threshold voltage transistors in the memory cells. Consequently, current leakage restricts the number of rows that may be included in a memory device that uses low threshold transistors. What is needed in the art is a way to accommodate more rows in a column of memory cells.